An arithmetic processing unit or device (a CPU chip or a microprocessor; hereinafter simply referred to as a processor) includes caches at a plurality of levels in order to improve memory access performance. The processor includes a plurality of arithmetic processing sections, cores, or circuits (CPU cores; hereinafter referred to as cores). The cores occupy and utilize respective first-level caches (L1 caches) as private caches. The processor further has upper-level caches shared by a plurality of the cores.
The processor also has one or a plurality of highest-level caches (last level caches: LLCs; hereinafter referred to as LLCs) included in the shared caches, and may have coherency control sections or circuits located outside the LLCs to maintain coherency among the caches.
International Publication Pamphlet No. WO 2013/084314 describes a processor having multi-level caches.